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ultra low power cmos sram 128k x 16 bit bs616uv2019 r0201-bs616uv2019 revision 1.4 oct. 2008 1 pb-free and green package materials are compliant to rohs ? features y wide v cc low operation voltage : c-grade : 1.8v ~ 3.6v i-grade : 1.9v ~ 3.6v y ultra low power consumption : v cc = 2.0v operation current : 10ma (max.) at 85ns 1ma (max.) at 1mhz standby current : 2/3ua (max.) at 70/85 o c v cc = 3.0v operation current : 13ma (max.) at 85ns 2ma (max.) at 1mhz standby current : 3/5ua (max.) at 70/85 o c y high speed access time : -85 85ns (max.) -10 100ns (max.) y automatic power down when chip is deselected y easy expansion with ce and oe options y i/o configuration x8/x16 selectable by lb and ub pin. y three state outputs and ttl compatible y fully static operation y data retention supply voltage as low as 1.5v ? description the bs616uv2019 is a high performance, ultra low power cmos static random access memory organized as 131,072 by 16 bits and operates form a wide range of 1.8v to 3.6v supply voltage. advanced cmos technology and ci rcuit techniques provide both high speed and low power features with maximum cmos standby current of 3/5ua at vcc=2/3v at 85 o c and maximum access time of 85/100ns. easy memory expansion is provided by an active low chip enable (ce) and active low output enable (oe) and three-state output drivers. the bs616uv2019 has an automatic power down feature, reducing the power consumption significant ly when chip is deselected. the bs616uv2019 is available in dice form, jedec standard 48-pin tsop type i package and 48-ball bga package. ? power consumption power dissipation standby (i ccsb1 , max) operating (i cc , max) v cc =3.0v v cc =2.0v product family operating temperature v cc =3.0v v cc =2.0v 1mhz f max. 1mhz f max. pkg type bs616uv2019dc dice bs616uv2019ac bga-48-0608 bs616uv2019tc commercial +0 o c to +70 o c 3.0ua 2.0ua 1.5ma 11ma 0.8ma 8ma tsop i-48 bs616uv2019ai bga-48-0608 bs616uv2019ti industrial -40 o c to +85 o c 5.0ua 3.0ua 2.0ma 13ma 1.0ma 10ma tsop i-48 ? pin configurations ? block diagram brilliance semiconductor, inc. reserves the right to change products and specifications without notice. g h f e d c b a 1 2 3 4 5 6 a 9 a 11 a 10 nc a 12 a 14 a 13 a 15 we d13 d5 d7 d6 nc a 16 a 7 vss vcc d12 d11 d4 d3 nc a 5 oe a 3 a 0 a 6 a 4 a 1 a 2 nc ub d10 d1 ce d2 d0 48-ball bga top view lb d8 d9 vss vcc d14 d15 nc nc a 8 address input buffer row decoder memory array 1024 x 2048 column i/o write driver sense am p column decoder address input buffer a 0 a 2 a 3 a 4 data input buffer control dq0 . . . . . . dq15 a6 a7 a8 a9 a10 a11 a15 a14 a13 a12 16 16 16 16 7 128 2048 1024 10 a 16 data output buffer a 1 ce2,ce we oe ub lb v cc v ss a 5 . . . . . . a15 a14 a13 a12 a11 a10 a9 a8 nc nc we ce2 nc ub lb nc nc a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 bs616uv2019tc bs616uv2019ti 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a16 nc gnd dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe gnd ce a0
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 2 ? pin descriptions name function a0-a16 address input these 17 address inputs select one of the 262,144 x 16 bit in the ram ce chip enable 1 input ce2 chip enable 2 input ce is active low and ce2 is active high . both chip enables must be active when data read from or write to the device. if ei ther chip enable is not active, the device is deselected and is in standby power mode. th e dq pins will be in the high impedance state when the device is deselected. (48b bga ignore ce2 pin) we write enable input the write enable input is active low and c ontrols read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, dat a will be present on the dq pins and they will be enabled. the dq pins will be in the high impendence state when oe is inactive. lb and ub data byte control input lower byte and upper byte data input/output control pins. dq0-dq15 data input/output ports 16 bi-directional ports are used to read data from or write data into the ram. v cc power supply v ss ground ? truth table mode ce ce2 (1) we oe lb ub dq0~dq7 dq8~dq15 v cc current h x x x x x high z high z i ccsb , i ccsb1 x l x x x x high z high z i ccsb , i ccsb1 chip de-selected (power down) x x x x h h high z high z i ccsb , i ccsb1 l h h h l x high z high z i cc output disabled l h h h x l high z high z i cc l l d out d out i cc h l high z d out i cc read l h h l l h d out high z i cc l l d in d in i cc h l x d in i cc write l h l x l h d in x i cc 1. 48bga ignore ce2 condition. 2. h means v ih ; l means v il ; x means don?t care (must be v ih or v il state)
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 3 ? absolute maximum ratings (1) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 (2) to 5.0 v t bias temperature under bias -40 to +125 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. ?2.0v in case of ac pulse width less than 30 ns. ? operating range rang ambient temperature v cc commercial 0 o c to + 70 o c 1.8v ~ 3.6v industrial -40 o c to + 85 o c 1.9v ~ 3.6v ? capacitance (1) (t a = 25 o c, f = 1.0mhz) symbol pamameter conditions max. units c in input capacitance v in = 0v 6 pf c io input/output capacitance v i/o = 0v 8 pf 1. this parameter is guaranteed and not 100% tested. ? dc electrical characteristics (t a = -40 o c to +85 o c) parameter name parameter test conditions min. typ. (1) max. units v cc power supply 1.9 -- 3.6 v v cc =2.0v 0.6 v il input low voltage v cc =3.0v -0.3 (2) -- 0.8 v v cc =2.0v 1.4 v ih input high voltage v cc =3.0v 2.2 -- v cc +0.3 (3) v i il input leakage current v in = 0v to v cc ce= v ih or ce2 (7) = v il -- -- 1 ua i lo output leakage current v i/o = 0v to v cc , ce= v ih or ce2 (7) = v il or oe = v ih -- -- 1 ua v cc = max, i ol = 0.1ma v cc =2.0v 0.2 v ol output low voltage v cc = max, i ol = 2.0ma v cc =3.0v -- -- 0.4 v v cc = min, i oh = -0.1ma v cc =2.0v 1.6 v oh output high voltage v cc = min, i oh = -1.0ma v cc =3.0v 2.4 -- -- v v cc =2.0v 10 i cc (5) operating power supply current ce = v il and ce2 (7) = v ih , i io = 0ma, f = f max (4) v cc =3.0v -- -- 13 ma v cc =2.0v 1.0 i cc1 operating power supply current ce = v il and ce2 (7) = v ih , i io = 0ma, f = 1mhz v cc =3.0v -- -- 2.0 ma v cc =2.0v 0.5 i ccsb standby current ? ttl ce = v ih or ce2 (7) = v il , i io = 0ma v cc =3.0v -- -- 1.0 ma v cc =2.0v 0.2 3.0 i ccsb1 (6) standby current ? cmos ce R v cc -0.2v or ce2 (7) Q 0.2v, v in R v cc -0.2v or v in Q 0.2v v cc =3.0v -- 0.3 5.0 ua 1. typical characteristics are at t a =25 o c and not 100% tested. 2. undershoot: -1.0v in case of pulse width less than 20 ns. 3. overshoot: v cc +1.0v in case of pulse width less than 20 ns. 4. f max =1/t rc. 5. i cc (max.) is 8ma/11ma at v cc =2.0v/3.0v and t a =70 o c. 6. i ccsb1(max.) is 2.0ua/3.0ua at v cc =2.0v/3.0v and t a =70 o c. 7. 48b bga ignore ce2 condition.
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 4 ? data retention characteristics (t a = -40 o c to +85 o c) symbol parameter test conditions min. typ. (1) max. units v dr v cc for data retention ce R v cc -0.2v or ce2 (4) Q 0.2v, v in R v cc -0.2v or v in Q 0.2v 1.5 -- -- v i ccdr (3) data retention current ce R v cc -0.2v or ce2 (4) Q 0.2v, v in R v cc -0.2v or v in Q 0.2v -- 0.1 1.0 ua t cdr chip deselect to data retention time 0 -- -- ns t r operation recovery time see retention waveform t rc (2) -- -- ns 1. v cc =1.5v, t a =25 o c and not 100% tested. 2. t rc = read cycle time. 3. i ccdr(max.) is 0.7ua at t a =70 o c. 4. 48b bga ignore ce2 condition ? low v cc data retention waveform (1) (ce controlled) ? low v cc data retention waveform (2) (ce2 controlled) ? ac test conditions (test load and input/output reference) input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc t clz , t olz , t chz , t ohz , t whz c l = 5pf+1ttl output load others c l = 30pf+1ttl 1. including jig and scope capacitance. ? key to switching waveforms waveform inputs outputs must be steady must be steady may change from ?h? to ?l? will be change from ?h? to ?l? may change from ?l? to ?h? will be change from ?l? to ?h? don?t care any change permitted change : state unknow does not apply center line is high inpedance ?off? state data retention mode v cc t cdr v cc t r v ih v ih ce R v cc - 0.2v v dr R 1.5v ce v cc ce2 data retention mode v cc t cdr v cc t r v il v il v dr R 1.5v ce2 Q 0.2v c l (1) 1 ttl output all input pulses 90% v cc gnd rise time: 1v/ns fall time: 1v/ns 90%
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 5 ? ac electrical characteristics (t a = -40 o c to +85 o c) read cycle cycle time : 85ns (v cc =1.9~3.6v) cycle time : 100ns (v cc =1.9~3.6v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t rc read cycle time 85 -- -- 100 -- -- ns t av q x t aa address access time -- -- 85 -- -- 100 ns t elqv1 t acs1 chip select access time (ce) -- -- 85 -- -- 100 ns t elqv2 t acs2 chip select access time (ce2) -- -- 85 -- -- 100 ns t blqv t ba data byte control access time (lb, ub) -- -- 85 -- -- 100 ns t glqv t oe output enable to output valid -- -- 40 -- -- 50 ns t elqx1 t clz1 chip select to output low z (ce) 15 -- -- 15 -- -- ns t elqx2 t clz2 chip select to output low z (ce2) 15 -- -- 15 -- -- ns t blqx t be data byte control to output low z (lb, ub) 15 -- -- 15 -- -- ns t glqx t olz output enable to output low z 15 -- -- 15 -- -- ns t ehqz1 t chz1 chip select to output high z (ce) -- -- 35 -- -- 40 ns t ehqz2 t chz2 chip select to output high z (ce2) -- -- 35 -- -- 40 ns t bhqz t bdo data byte control to output high z (lb, ub) -- -- 35 -- -- 40 ns t ghqz t ohz output enable to output high z -- -- 30 -- -- 35 ns t av q x t oh data hold from address change 15 -- -- 15 -- -- ns ? switching waveforms (read cycle) read cycle 1 (1,2,4) t rc t oh t aa d out address t oh
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 6 read cycle 2 (1,3,4) read cycle 3 (1, 4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce = v il and ce2= v ih . 3. address valid prior to or coincident with ce transition low and/or ce2 transition high. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. 6. 48b bga ignore this parameters related to ce2. t clz (5 , 6) d out ce2 ce t a cs2 (6) t a cs1 t chz (5 , 6) t oh t rc t oe t be t bdo d out ce oe address t clz (5 , 6) t a cs1 t chz (1 , 5 , 6) t ohz (5) t olz t aa lb, ub t b a ce2 t acs2 (6)
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 7 ? ac electrical characteristics (t a = -40 o c to +85 o c) write cycle cycle time : 85ns (v cc =1.9~3.6v) cycle time : 100ns (v cc =1.9~3.6v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t wc write cycle time 85 -- -- 100 -- -- ns t av w l t as address set up time 0 -- -- 0 -- -- ns t av w h t aw address valid to end of write 85 -- -- 100 -- -- ns t elwh t cw chip select to end of write 85 -- -- 100 -- -- ns t blwh t bw data byte control to end of write (lb, ub) 50 -- -- 70 -- -- ns t wlwh t wp write pulse width 40 -- -- 50 -- -- ns t whax1 t wr1 write recovery time (ce, we) 0 -- -- 0 -- -- ns t whax2 t wr2 write recovery time (ce2) 0 -- -- 0 -- -- ns t wlqz t whz write to output high z -- -- 35 -- -- 40 ns t dvwh t dw data to write time overlap 35 -- -- 40 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 35 -- -- 40 ns t whqx t ow end of write to output active 10 -- -- 10 -- -- ns ? switching waveforms (write cycle) write cycle 1 (1) t wc t wr1 (3) t cw (11) t wp (2) t aw t ohz (4 , 10) t as t wr2 (3) t dh t dw d in d out we lb, ub ce oe address (5) t bw t cw (11) ce2 (5 , 12 )
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 8 write cycle 2 (1,6) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is def ined by the overlap of ce and ce2 active and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high or ce2 going low at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition or the ce2 high tr ansition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low and ce2 is high during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low or ce2 going high to the end of write. 12. 48b bga ignore this parameters related to ce2. t wc t cw (11) t wp (2) t aw t whz (4 , 10) t as t wr (3) t dh t dw d in d out we lb, ub ce address (5) t ow (7) (8) (8 , 9) t bw ( 5 ) ce2 (5 , 12 )
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 9 ? ordering information note: bsi (brilliance semiconductor inc.) assumes no responsibility for the application or use of any product or circuit described he rein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be exp ected to result in significant injury or death, including life- support systems and critical medical instruments. ? package dimensions 1 2 2 d 1 hd 4 section a-a base metal with plating c c b1 b 0.0236 0.006 0.020 0.004 0.004 ~ 0.006 0.004 ~ 0.008 0.008 0.001 0.009 0.002 0.0433 0.004 0 ~8 0.004 max. 0.0315 0.708 0.008 0.472 0.004 0.645 0.004 0.039 0.002 0.004 0.002 2 "a" 2 seating 4 12 (2x) e b e 12 (2x) d y l1 y l hd e e symbo b c1 b1 c a2 a1 a unit 16.40 0.10 0.50 0.10 0.80 0.10 0.60 0.15 18.00 0.20 11.80 0.10 0 ~8 0.1 max. 0.10 ~ 0.16 0.10 ~ 0.21 0.20 0.03 0.22 0.05 1.00 0.05 0.10 0.05 1.10 0.10 mm inch 12 (2x) "a" detail view l1 gauge plane a1 a a2 seating plane 12 (2x) l a a tsop i-48 pin package d: dice a: bga-48-0608 t : t so pi - 48 bs616uv2019 x x z y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 85: 85ns 10: 100ns pkg material g: green, rohs compliant p: pb free, rohs compliant
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 10 ? package dimensions (continued) 48 mini-bga (6 x 8mm) d1 view a 1.2 max. e e1 1: controlling dimensio ns are in millimeters. 2: pin#1 dot marking by laser or pad print. 3: symbol "n" is the number of solder balls. ball pitch e = 0.75 d 8.0 6.0 e n 48 3.75 e1 d1 5.25
bs616u v 2019 r0201-bs616uv2019 revision 1.4 oct. 2008 11 ? revision history revision no. history draft date remark 1.2 add icc1 characteristic parameter jan. 13, 2006 1.3 change i-grade operation temperature range may. 25, 2006 - from ?25 o c to ?40 o c 1.4 typical value of standby current is replaced by oct. 31, 2008 maximum value in featues and description section remove ?-: normal? (leaded) pkg material in ordering information

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